# Raspberry Pi: ARM-side cache details

## Introduction

On ARM platforms, there would be some caches up to 7 (inclusive). Policies, sizes and characteristics of them can be obtained by accessing CP15 coprocessor on ARM, which privides architecture and feature information.

To read/write from/to registers of CP15, MRC and MCR instructions are used, respectively. The registers are selected by CRn, CRm, opc1 and opc2 arguments of the instructions. Table 1 shows a part of the registers related to caches. To be more precise, MRC p15, opc1, Rt, CRn, CRm, opc2 reads from a CP15 register and writes the content of it to an ARM register Rt, and MCR p15, opc1, Rt, CRn, CRm, opc2 writes the content of an ARM register Rt to a CP15 register.

Table 1. A part of CP15 registers related to caches
Name CRn CRm opc1 opc2 Description
CCSIDR c0 c0 1 0 Cache size ID register
CLIDR c0 c0 1 1 Cache level ID register
CSSELR c0 c0 2 0 Cache size selection register

## Environment

Our experiments in this article are carried out on these boards:

• Raspberry Pi 1 Model B v2.0
• Raspberry Pi 2 Model B v1.1
• Raspberry Pi 3 Model B v1.2
They all have ARM CPUs and thus have CP15 coprocessor.

Accessing CP15 registers needs PL1 privilege, which is normally the one at which operating system runs. So we wrote a Linux driver which accesses CP15 registers on loading.

## Obtaining cache information

First, we obtain the number of caches the ARM CPUs implement. The CLIDR register bits [$3(n-1)+2$:$3(n-1)$] indicates whether level-$n$ cache exists and the type of that if it does.

It is shown that Raspberry Pi 2 and 3 have level-1 and level-2 caches: the former is separated to instruction and data ones and the latter is unified.

In the next, we obtain the characteristics of the caches. The CCSIDR register shows policies and sizes of the caches selected in the CSSELR register. Bit $0$ of the CSSELR register indicates which type of the cache is selected ($0$ means data or unified cache and $1$ means instruction cache). And bits [$3$:$1$] indicates the level of the cache $-1$ selected (e.g., $0\mathrm{b}000$ indicates level-1 cache).

The results are shown on Table 2, Table 3 and Table 4.

Table 3. Raspberry Pi 2
L1C data L1C insn. L2C
Write-through not supported not supported not supported
Write-back supported not supported supported
Read-alloc supported supported supported
Write-alloc supported not supported supported
Num. of sets 128 512 1024
Associativity 4 2 8
Line size 16 8 16

Table 4. Raspberry Pi 3
L1C data L1C insn. L2C
Write-through not supported not supported not supported
Write-back supported not supported supported
Read-alloc supported supported supported
Write-alloc supported not supported supported
Num. of sets 128 256 512
Associativity 4 2 16
Line size 16 16 16

## Reference

• ARM, "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition"